Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates

To overcome the “von Neumann bottleneck,” methods to compute in memory are being researched many emerging technologies, including resistive RAMs (ReRAMs). Majority logic is efficient for synthesizing arithmetic circuits when compared NAND/NOR/IMPLY logic. In this work, we propose a method implement majority gate transistor-accessed ReRAM array during READ operation. Together with NOT gate, which also implemented memory, proposed forms functionally complete Boolean logic, capable of implementing any digital Computing simplified sequence and WRITE operations does not require major modifications peripheral circuitry array. While have been recently latency in-memory adders as such exorbitant ( O( n)). Parallel-prefix (PP) use prefix computation accelerate addition conventional CMOS-based adders. By exploiting parallel-friendly nature regular structure array, it demonstrated how PP can be O(log( n)) latency. The technique incurs 4·log( n)+6 n-bit energy-efficient due absence sneak currents 1Transistor-1Resistor configuration.